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ISL29003
TABLE 2. WRITE ONLY REGISTERS
At Mode2, the mux directs the current of Diode2 only to
ADDRESS
b1xxx_xxxx
REGISTER
NAME
sync_iic
FUNCTIONS/
DESCRIPTION
Writing a logic 1 to this address bit
ends the current ADC-integration
and starts another. Used only with
External Timing Mode.
the ADC. Mode3 is a sequential Mode1 and Mode2 with
an internal subtract function (Diode1 - Diode2).
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
BITS 3:2
MODE
0:0
MODE1. ADC integrates or converts Diode1 only.
Current is converted to an n-bit unsigned data.*
bx1xx_xxxx
clar_int
Writing a logic 1 to this address bit
clears the interrupt.
0:1
MODE2. ADC integrates or coverts Diode2 only.
Current is converted to an n-bit unsigned data.*
Command Register 00(hex)
The Read/Write command register has five functions:
1. Enable; Bit 7. This function either resets the ADC or
enables the ADC in normal operation. A logic 0 disables
1:0
1:1
MODE3. A sequential MODE1 then MODE2
operation. The difference current is an (n-1) signed
data.*
No Operation.
ADC to reset-mode. A logic 1 enables adc to normal
operation.
TABLE 3. ENABLE
*n = 4, 8, 12,16 depending on the number of clock cycles
function.
5. Width; Bits 1 and 0. This function determines the number
BIT 7
0
1
OPERATION
Disable ADC-Core to Reset-Mode (default)
Enable ADC-Core to Normal Operation
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device; it also changes the integration time, which is
the period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
2. ADCPD; Bit 6. This function puts the device in a
power-down mode. A logic 0 puts the device in normal
measurement.
TABLE 7. WIDTH
operation. A logic 1 powers down the device.
TABLE 4. ADCPD
BITS 1:0
0:0
NUMBER OF CLOCK CYCLES
2 16 = 65,536
BIT 6
0
1
OPERATION
Normal Operation (default)
Power-Down
0:1
1:0
1:1
2 12 = 4,096
2 8 = 256
2 4 = 16
For proper shut down operation, it is recommended to
disable ADC first then disable the chip. Specifically, the user
should first send I 2 C command with Bit 7 = 0 and then send
I 2 C command with Bit 6 = 1.
3. Timing Mode; Bit 5. This function determines whether the
integration time is done internally or externally. In Internal
Control Register 01(hex)
The Read/Write control register has three functions:
1. Interrupt flag; Bit 5. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds
have been triggered, and logic low when not yet
triggered. Writing a logic low clears/resets the status bit.
Timing Mode, integration time is determined by an
internal dual speed oscillator (f OSC ), and the n-bit (n = 4,
8, 12,16) counter inside the ADC. In External Timing
Mode, integration time is determined by the time between
two consecutive external-sync sync_iic pulse commands.
TABLE 5. TIMING MODE
BIT 5
0
1
TABLE 8. INTERRUPT FLAG
OPERATION
Interrupt is cleared or not triggered yet
Interrupt is triggered
BIT 5
0
1
OPERATION
Internal Timing Mode. Integration time is internally
timed determined by f OSC , REXT, and number of
clock cycles.
External Timing Mode. Integration time is externally
timed by the I 2 C host.
2. Range/Gain; Bits 3 and 2. The Full Scale Range can be
adjusted by an external resistor R EXT and/or it can be
adjusted via I 2 C using the Gain/Range function.
Gain/Range has four possible values, Range(k) where k
is 1 through 4. Table 9 lists the possible values of
Range(k) and the resulting FSR for some typical value
R EXT resistors.
4. Photodiode Select Mode; Bits 3 and 2. This function
controls the mux attached to the two photodiodes. At
Mode1, the mux directs the current of Diode1 to the ADC.
6
FN7464.6
November 17, 2011
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